Method and apparatus for clock and data alignment that reduces power consumption
US12176908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Dec 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; a second stage including a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators. The subject disclosure further includes the second number of phase rotators being less than the first number of phase rotators, and a total number of bits dedicated to phase selection being split across the first stage and the second stage. Other embodiments are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.