Microelectronic devices with tiered decks of aligned pillars exhibiting bending and related methods
US12178045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jan 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
Abstract
Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.