Circuit with load jump mitigation
US12181912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jun 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/324
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit having load jump mitigation, including: circuit processing stages arranged in a pipeline configuration and operable based on respective stage clock signals; and clock control circuits respectively connected to the circuit processing stages to control the respective stage clock signals. Each of the clock control circuits is operable to: enable the respective stage clock signal in response to receiving a data in signal representing that the respective circuit processing stage begins to receive valid data for processing; disable the respective stage clock signal based on a predetermined respective circuit processing stage processing delay having elapsed since the respective circuit processing stage received any valid data; and enable a next of the clock control circuits, which is connected to a next of the circuit processing stages, based on the predetermined respective circuit processing stage processing delay having elapsed since the respective stage clock signal was enabled, indicating that the respective circuit processing stage is beginning to send the processed valid data to the next circuit processing stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.