Executing a composite scalar-vector VLIW instruction having a repeat field
US12182576B2 · kind B2 · utility
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6References
19Claims
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Key dates
| Filing date | Dec 31, 2019 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Dec 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the composite VLIW instruction to perform the operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.