Hans M. Jacobson
77Patents
9h-index
56Co-inventors
77Inventor score
Filing activity: Aug 20, 2001 → Dec 31, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7076682B2 | Synchronous pipeline with normally transparent pipeline stages | Physics | 24 | Expired |
| US7065665B2 | Interlocked synchronous pipeline clock gating | Emerging Cross-Sectional Technologies | 20 | Expired |
| US6946869B2 | Method and structure for short range leakage control in pipelined circuits | Electricity | 19 | Expired |
| US7076681B2 | Processor with demand-driven clock throttling power reduction | Emerging Cross-Sectional Technologies | 18 | Expired |
| US9268704B2 | Low latency data exchange | Emerging Cross-Sectional Technologies | 14 | Active |
| US7447923B2 | Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power | Emerging Cross-Sectional Technologies | 12 | Expired |
| US7930578B2 | Method and system of peak power enforcement via autonomous token-based control and management | Emerging Cross-Sectional Technologies | 11 | Active |
| US8424006B2 | Task assignment on heterogeneous three-dimensional/stacked microarchitectures | Emerging Cross-Sectional Technologies | 10 | Active |
| US7945765B2 | Method and structure for asynchronous skip-ahead in synchronous pipelines | Physics | 10 | Active |
| US7100144B2 | System and method for topology selection to minimize leakage power during synthesis | Physics | 9 | Expired |
| US7685457B2 | Interlocked synchronous pipeline clock gating | Emerging Cross-Sectional Technologies | 8 | Active |
| US9110778B2 | Address generation in an active memory device | Emerging Cross-Sectional Technologies | 7 | Active |
| US9354884B2 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Physics | 6 | Active |
| US6512397B1 | Circuit structures and methods for high-speed low-power select arbitration | Emerging Cross-Sectional Technologies | 6 | Expired |
| US7308593B2 | Interlocked synchronous pipeline clock gating | Emerging Cross-Sectional Technologies | 6 | Expired |
| US8564262B2 | Voltage regulator module with power gating and bypass | Physics | 6 | Active |
| US8073669B2 | Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design | Emerging Cross-Sectional Technologies | 5 | Active |
| US8176354B2 | Wave pipeline with selectively opaque register stages | Physics | 5 | Active |
| US6608771B2 | Low-power circuit structures and methods for content addressable memories and random access memories | Physics | 4 | Expired |
| US9298654B2 | Local bypass in memory computing | Emerging Cross-Sectional Technologies | 4 | Active |
| US8244515B2 | Structure for detecting clock gating opportunities in a pipelined electronic circuit design | Emerging Cross-Sectional Technologies | 4 | Active |
| US10114652B2 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Physics | 3 | Active |
| US7475227B2 | Method of stalling one or more stages in an interlocked synchronous pipeline | Emerging Cross-Sectional Technologies | 3 | Expired |
| US9354943B2 | Power management for multi-core processing systems | Emerging Cross-Sectional Technologies | 3 | Active |
| US9405711B2 | On-chip traffic prioritization in memory | Emerging Cross-Sectional Technologies | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.