High-speed multi-port memory supporting collision
US12183393B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Mar 12, 2024 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Mar 12, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.