Memory circuits and devices, and methods thereof
US12183397B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Dec 17, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jun 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.