Manufacturing method of semiconductor structure including complementary first and second mask patterns
US12183585B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jun 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0272
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a manufacturing method of a semiconductor structure, including: providing a substrate; forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions; forming several discrete bitlines on the active regions; forming a sacrificial layer between adjacent bitlines; forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact structures. The embodiment of the present disclosure is beneficial to reducing the manufacturing cost of the semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.