Selective underfill assembly and method therefor
US12183595B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 12, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Mar 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.