Semiconductor device with enhanced thermal dissipation and method for making the same
US12183655B2 · kind B2 · utility
0Cited by
16References
20Claims
0Family size
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Key dates
| Filing date | Jul 26, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Dec 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.