Semiconductor package and method for manufacturing the same
US12183704B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 11, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor package including a first semiconductor chip having a bottom surface adjacent to a first active layer and an top surface opposite to the bottom surface; a first adhesive layer disposed on the top surface of the first semiconductor chip; a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer; a first conductive post disposed outside the first semiconductor chip; a redistribution structure disposed under the first semiconductor chip and including a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern; and a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure. Also, a top surface of the molding layer, a top surface of the conductive post, and a top surface of the first adhesive layer may be coplanar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.