Semiconductor devices comprising crack preventing layers and data storage systems including the same
US12185543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jun 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.