Asynchronous communication protocol compatible with synchronous DDR protocol
US12189546B2 · kind B2 · utility
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33References
20Claims
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Key dates
| Filing date | Jul 25, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jul 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.