Skip program verify for dynamic start voltage sampling
US12189955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Dec 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5624
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Skip program verify for dynamic start voltage (DSV) sampling reduces latency of a program operation on multi-level cell (MLC) memory having at least two pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND device. The NAND device skips program verifies corresponding to higher levels of voltage thresholds during DSV sampling. As a result, the NAND device can reduce a total program time (tPROG) to program the MLC memory, and determine the dynamic start program voltage more quickly. The NAND device can improve an effective TLC NAND tPROG by as much as 2% without impacting the placement of the first sub-block being programmed. The skipped program verifies corresponding to the higher levels of voltage thresholds are resumed as soon as DSV sampling is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.