Memory device with dummy word line, system and method for programming thereof
US12190955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array including memory blocks and a peripheral circuit coupled to the memory cell array. Each memory block includes memory strings each including dummy cells and select transistors, bit lines coupled to the memory strings, select lines including first select lines and second select lines, and one or more dummy word lines. Each select line coupled to the select transistors. The first select lines are closer to the bit lines than the second select lines. Each dummy word line is coupled to the respective dummy cells. The dummy word lines include a first dummy word line adjacent to either the first select lines or the second select lines. The peripheral circuit is configured to apply a turn-on voltage to all the first select lines, and apply a program voltage to the first dummy word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.