Nonvolatile memory device preventing overshoot of internal voltage and method of operating nonvolatile memory device
US12190964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.