Multi-step isotropic etch patterning of thick copper layers for forming high aspect-ratio conductors
US12191161B2 · kind B2 · utility
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3References
25Claims
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Key dates
| Filing date | Dec 23, 2020 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | May 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49827
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device, comprising a substrate comprising a dielectric material and a conductor on or within the dielectric material of the substrate. The conductor comprises a first portion comprising a first sloped sidewall, wherein a first base width of the first portion is greater than a first top width of the first portion. The conductor also comprises a second portion over the first portion, the second portion comprising a second sloped sidewall, wherein a second base width of the upper portion is greater than both a second top width of the second portion and the first top width of the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.