Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance
US12191196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Nov 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a source on a first side of a gate. The semiconductor device may include a drain on a second side of the gate, where the second side of the gate is opposite to the first side of the gate. The semiconductor device may include a first contact over the source. The semiconductor device may include a second contact over the drain. The semiconductor device may include an air gap over the gate between at least the first contact and the second contact. The semiconductor device may include at least two dielectric materials in each of a region between the air gap and the first contact and a region between the air gap and the second contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.