Linear prediction to suppress spurs in a digital phase-locked loop
US12191866B2 · kind B2 · utility
0Cited by
7References
24Claims
0Family size
Inventor
Key dates
| Filing date | Sep 3, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Mar 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0069
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique uses linear prediction to determine the location of spurious content in a digital phase-locked loop and suppresses the spurious content from propagating to the clock output. In at least one embodiment, the technique implements an iterative (e.g., recursive) computation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.