Low resistance via contacts in a memory device
US12193341B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Aug 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/882
Abstract
Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.