Efficient hard decoding of error correction code via extrinsic bit information
US12197283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2023 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Mar 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects can include selecting memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second plurality of pages including corresponding second pluralities of bits, obtaining, based on the second pluralities of bits, extrinsic page information for a proposed error solution including a third plurality of bits indicating a reliability of respective bits of the first plurality of bits, and rejecting, in response to a determination that the proposed error solution indicates a modification to a reliable bit among the first plurality of bits, the proposed error solution to eliminate a false correction of the first plurality of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.