Patent · US Active

Hardware offload circuitry

US12197601B2 · kind B2 · utility

0Cited by

0References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ren Wang · Portland, US
Sameh Gobriel · Hillsboro, US
Somnath Paul · Milpitas, US
Yipeng Wang · Houston, US
Priya Autee · Chandler, US
Abhirupa Layek · Chandler, US
Shaman Narayana · Chandler, US
Edwin Verplanke · Chandler, US
Mrittika Ganguli · Tempe, US
Jr-Shian Tsai · Beaverton, US
Anton Alexandrovich Sorokin · Portland, US
Suvadeep Banerjee · Santa Clara, US
Abhijit Davare · Hillsboro, US
Desmond Kirkpatrick · Portland, US
Rajesh M. Sankaran · Portland, US
Jaykant B. Timbadiya · Kodinar, IN
Sriram Kabisthalam Muthukumar · Coimbatore, IN
Narayan Ranganathan · Bengaluru, IN
Nalini Murari · Hillsboro, US
Brinda Ganesh · Portland, US
Nilesh Jain · Portland, US

Key dates

Filing date	Dec 22, 2021
Grant date	Jan 14, 2025
Priority date	—
Expiry date	May 13, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F2209/509
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.