Memory device for increasing speed of soft-program operation
US12198770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jun 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.