Semiconductor device, semiconductor package and method of manufacturing the same
US12199056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | May 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.