Plugs for interconnect lines for advanced integrated circuit structure fabrication
US12199168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Feb 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.