Low gate-count and high throughput Reed-Solomon decoding
US12199636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Mar 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/293
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of operation for a Reed-Solomon decoder includes receiving partial input data of symbols of a Reed-Solomon codeword; updating Reed-Solomon syndromes and error location polynomial coefficients based on the partial input data; maintaining the Reed-Solomon syndromes and the error location polynomial coefficients in a memory prior to starting activation of Reed-Solomon decoding; and inputting the Reed-Solomon syndromes and the error location polynomial coefficients to a first activation of Reed-Solomon decoding including calculating an initial error evaluator polynomial as a first error evaluator polynomial, performing error detection based on the first error evaluator polynomial to determine presence and location of errors in an input Reed-Solomon codeword, and updating the error location polynomial when errors are found in the input Reed-Solomon codeword. The error location polynomial coefficients in the memory are updated during each activation of Reed-Solomon decoding when at least one error is identified in the Reed-Solomon codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.