Multiple plane programming with quick plane programming termination and lagging plane boosting
US12204422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jul 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.