Bayesian neural network with resistive memory hardware accelerator and method for programming the same
US12205020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2021 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Nov 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Bayesian neural network including an input layer, and, an output layer, and, possibly, one or more hidden layer(s). Each neuron of a layer is connected at its input with a plurality of synapses, the synapses of the plurality being implemented as a RRAM array constituted of cells, each column of the array being associated with a synapse and each row of the array being associated with an instance of the set of synaptic coefficients, the cells of a row of the RRAM being programmed during a SET operation with respective programming current intensities, the programming intensity of a cell being derived from the median value of a Gaussian component obtained by GMM decomposition into Gaussian components of the marginal posterior probability of the corresponding synaptic coefficient, once the BNN model has been trained on a training dataset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.