Semiconductor packages with chiplets coupled to a memory device
US12205924B2 · kind B2 · utility
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1References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Feb 21, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jul 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15313
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.