Semiconductor package having package substrate
US12205925B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jan 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.