Stacked diode with side passivation and method of making the same
US12206030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Mar 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process flow for a stacked power diode and design of the resulting diode is disclosed. Blanket epitaxy over heavy doped wafers is performed. By controlling dopant addition during epitaxy, desired n-type, diode base, and p-type doping profiles and thicknesses achieved. V-groove pattern if formed on wafers by depositing mask film, lithography and anisotropic etch. Islands surrounded by V-grooves define individual diodes. V-grooves serve as side insulation. Next, oxidation step passivates V-grooves. Further, the mask film is stripped to open diode contact areas on both sides of wafers. Next high melting point metal and low melting point metal films are selectively electroplated on all open silicon surfaces. Stacking is performed on wafer level by bonding of desired wafer count by solid-liquid interdiffusion process. Wafer stacks are sawed into individual stacked diode dies along outer slopes of V-grooves. Final stacked devices can be used as DSRD—drift step recovery diodes. Compared to DSRDs made by known methods, better fabrication yield and higher pulse power electrical performance is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.