Processing for vector load or store micro-operation with inactive mask elements
US12210874B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jun 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.