Implicit global pointer relative addressing for global memory access
US12210876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Mar 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.