Memory device and program operation thereof
US12211554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | May 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, a system, and a method for operating the memory device are provided. The memory device includes a first memory string and a peripheral circuit. The first memory string includes a first drain, a first drain select gate (DSG) transistor, a first drain dummy transistor between the first drain and the first DSG transistor, and a plurality of first memory cells. A first drain dummy line is coupled to the first drain dummy transistor, and a first DSG line is coupled to the first DSG transistor. The peripheral circuit is configured to, in a program operation, apply a first DSG voltage to the first DSG line and apply a first drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The first drain dummy line voltage is greater than the first DSG voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.