Test circuit and method for reading data from a memory device during memory dump
US12211570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jul 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.