SRAM with tracking circuitry for reducing active power
US12211587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jun 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.