Electronic package and manufacturing method thereof
US12211776B2 · kind B2 · utility
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17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Oct 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.