Semiconductor device and a method for fabricating the same
US12211845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Dec 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.