Low-voltage differential signaling (LVDS) transmitter circuit
US12212318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jan 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/028
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.