Inventor · Noida, IN

Paras Garg

15Patents

6h-index

21Co-inventors

62Inventor score

Filing activity: Jun 7, 2005 → Jan 18, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7495483B2	Input buffer for CMOS integrated circuits	Electricity	13	Active
US7368976B2	Method and apparatus for providing compensation against temperature, process and supply voltage variation	Electricity	11	Expired
US7425849B2	Low noise output buffer capable of operating at high speeds	Electricity	11	Expired
US7164305B2	High-voltage tolerant input buffer circuit	Electricity	8	Expired
US9473135B2	Driver circuit including driver transistors with controlled body biasing	Electricity	7	Active
US7902885B2	Compensated output buffer for improving slew control rate	Electricity	7	Active
US8207754B2	Architecture for efficient usage of IO	Electricity	4	Active
US8981817B2	Operating conditions compensation circuit	Electricity	3	Active
US8253437B2	Reduction of signal skew	Electricity	2	Active
US7768311B2	Suppressing ringing in high speed CMOS output buffers driving transmission line load	Electricity	2	Active
US10530366B1	Low voltage differential signaling fault detector	Physics	1	Active
US11176649B1	System and method of identifying presence of digital ghosting artifacts in videos	Physics	0	Active
US12212318B2	Low-voltage differential signaling (LVDS) transmitter circuit	Electricity	0	Active
US11223354B2	Low current, wide range input common mode LVDS receiver devices and methods	Electricity	0	Active
US10664717B2	System and method for searching an image within another image	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.