Syndrome decoder circuit
US12212338B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Oct 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1108
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X−1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.