Semiconductor package for improving power integrity characteristics
US12213256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Apr 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.