Method of improving programming operations in 3D NAND systems
US12216907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2022 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Dec 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.