Semiconductor device with improved performance in operation and improved flexibility in the arrangement of power chips

US12218029B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Edward Fuergut · Nuremberg, DE
• Anton Mauder · Kolbermoor, DE
• Stephan Voss · Munich, DE
• Martin Gruber · Schwandorf, DE

Key dates

• Filing date: May 25, 2022
• Grant date: Feb 4, 2025
• Expiry date: Jul 28, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.