Method of forming an integrated circuit device having an etch-stop layer between metal wires
US12218054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2022 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Jun 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.