Memory controller and method for controlling output of debug messages
US12222856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2023 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Jun 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.