Methods and circuits of spatial alignment
US12223010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Mar 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.