Patent · US Active

Enhanced write performance utilizing program interleave

US12223208B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Daniel J. Hubbard · Boise, US
Roy Leonard · San Jose, US

Key dates

Filing date	Nov 20, 2023
Grant date	Feb 11, 2025
Priority date	—
Expiry date	Nov 20, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG11C2211/5641
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.