Adaptive memory registers
US12223995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Sep 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.