Staggered active bitline sensing
US12224015B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 21, 2021 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Jun 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.